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W39L040A Data Sheet 512K x 8 CMOS FLASH MEMORY
Table of Contents1. 2. 3. 4. 5. 6. GENERAL DESCRIPTION ......................................................................................................... 3 FEATURES ................................................................................................................................. 3 PIN CONFIGURATIONS ............................................................................................................ 4 BLOCK DIAGRAM ...................................................................................................................... 4 PIN DESCRIPTION..................................................................................................................... 4 FUNCTIONAL DESCRIPTION ................................................................................................... 5 6.1 Device Bus Operation..................................................................................................... 5
6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 Read Mode.......................................................................................................................5 Write Mode .......................................................................................................................5 Standby Mode ..................................................................................................................5 Output Disable Mode........................................................................................................5 Auto-select Mode..............................................................................................................5
6.2
Data Protection ............................................................................................................... 6
6.2.1 6.2.2 6.2.3 6.2.4 Low VDD Inhibit................................................................................................................6 Write Pulse "Glitch" Protection .........................................................................................6 Logical Inhibit ...................................................................................................................6 Power-up Write and Read Inhibit......................................................................................6
6.3
Command Definitions ..................................................................................................... 6
6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 Read Command ...............................................................................................................6 Auto-select Command ......................................................................................................7 Byte Program Command ..................................................................................................7 Chip Erase Command ......................................................................................................7 Sector Erase Command ...................................................................................................8
6.4
Write Operation Status ................................................................................................... 8
6.4.1 6.4.2 DQ7: #Data Polling...........................................................................................................8 DQ6: Toggle Bit................................................................................................................9
6.5
Table of Operating Modes .............................................................................................. 9
6.5.1 6.5.2 6.5.3 6.5.4 Device Bus Operations.....................................................................................................9 Auto-select Codes (High Voltage Method) .......................................................................9 Sector Address Table .....................................................................................................10 Command Definitions .....................................................................................................10
6.6 6.7
Embedded Programming Algorithm ............................................................................. 11 Embedded Erase Algorithm.......................................................................................... 12 Publication Release Date:April 14, 2005 Revision A3
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W39L040A
6.8 6.9 7. 7.1 7.2 7.3 7.4 Embedded #Data Polling Algorithm.............................................................................. 13 Embedded Toggle Bit Algorithm ................................................................................... 13 Absolute Maximum Ratings .......................................................................................... 14 DC Operating Characteristics....................................................................................... 14 Pin Capacitance............................................................................................................ 14 AC Characteristics ........................................................................................................ 15
7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 AC Test Conditions.........................................................................................................15 AC Test Load and Waveform .........................................................................................15 Read Cycle Timing Parameters......................................................................................16 Erase/Program Cycle Timing Parameters ......................................................................16 Power-up Timing ............................................................................................................17 #Data Polling and Toggle Bit Timing Parameters ...........................................................17
ELECTRICAL CHARACTERISTICS......................................................................................... 14
8.
TIMING WAVEFORMS ............................................................................................................. 18 8.1 8.2 8.3 8.4 8.5 8.6 8.7 Read Cycle Timing Diagram......................................................................................... 18 #WE Controlled Command Write Cycle Timing Diagram............................................. 18 #CE Controlled Command Write Cycle Timing Diagram.............................................. 19 Chip Erase Timing Diagram ......................................................................................... 19 Sector Erase Timing Diagram ...................................................................................... 20 #Data Polling Timing Diagram ...................................................................................... 20 Toggle Bit Timing Diagram ........................................................................................... 21
9. 10. 11.
ORDERING INFORMATION .................................................................................................... 22 HOW TO READ THE TOP MARKING...................................................................................... 23 PACKAGE DIMENSIONS ......................................................................................................... 24 11.1 11.2 11.3 11.4 32L PLCC ..................................................................................................................... 24 32L PDIP....................................................................................................................... 24 32L TSOP (8 x 20 mm)................................................................................................. 25 32L STSOP (8 x 14 mm) .............................................................................................. 25
12.
VERSION HISTORY ................................................................................................................. 26
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W39L040A
1. GENERAL DESCRIPTION
The W39L040A is a 4Mbit, 3V/3.3V CMOS flash memory organized as 512K x 8 bits. For flexible erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes. The byte-wide (x 8) data appears on DQ7 - DQ0. The device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is not required. The unique cell architecture of the W39L040A results in fast program/erase operations with extremely low current consumption (compared to other comparable 3.3-volt flash memory products). The device can also be programmed and erased by using standard EPROM programmers.
2. FEATURES
*
3V/3.3-Volt Read/Erase/Program Operations - 3.0 ~ 3.6V for 70nS - 2.7 ~ 3.6V for 90nS
* * *
Typical program/erase cycles: 10K Twenty-year data retention Low power consumption - Active read current: 7 mA at 5MHz (typ.) - Active program/erase current: 15 mA at 5MHz (typ.) - Standby current: 0.2 A (typ.) End of program detection - Software method: Toggle bit/#Data polling JEDEC standard byte-wide pinouts Available packages: 32-pin PLCC Lead free, 32-pin STSOP (8 x 14 mm) Lead free, 32-pin PDIP and 32-pin TSOP (8 x 20 mm)
*
Fast Program operation: - Byte-by-Byte programming: 9 S (typ.) Fast Erase operation: - Chip Erase cycle time: 6 S (typ.) - Sector Erase cycle time: 0.7 S (typ.)
* * *
*
*
* *
Read access time: 70/90 nS 8 Even sectors with 64K bytes Any individual sector can be erased
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3. PIN CONFIGURATIONS
A 1 2 4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A 1 5 3 A 1 6 2 A 1 8 1 V D D # W E A 1 7
4. BLOCK DIAGRAM
32 31 30 29 28 27 26 A14 A13 A8 A9 A11 #OE A10 #CE DQ7
VDD VSS #CE #OE #WE
OUTPUT BUFFER
DQ0 .
.
32L PLCC
CONTROL
25 24 23 22 21
DQ7
D Q 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
D Q 2
VD SQ S3
D Q 4
D Q 5
D Q 6 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A0
#OE A10 #CE DQ7 DQ6 DQ5 DQ4 DQ3 V SS DQ2 DQ1 DQ0 A0 A1 A2 A3
A11 A9 A8 A13 A14 A17 #WE VDD A18 A16 A15 A12 A7 A6 A5 A4
. . A18
DECODER
CORE ARRAY
32L STSOP and 32L TSOP
5. PIN DESCRIPTION
SYMBOL PIN NAME
A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 Vss
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27
VDD #WE A17 A14 A13 A8 A9 A11 #OE A10 #CE DQ7 DQ6 DQ5 DQ4 DQ3
A0 - A18 DQ0 - DQ7 #CE #OE #WE VDD VSS
Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply Ground
32-pin DIP
26 25 24 23 22 21 20 19 18 17
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W39L040A
6. FUNCTIONAL DESCRIPTION
6.1 Device Bus Operation
6.1.1 Read Mode
The read operation of the W39L040A is controlled by #CE and #OE, both of which have to be low for the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is de-selected and only standby power will be consumed. #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either #CE or #OE is high. Refer to the timing waveforms for further details.
6.1.2
Write Mode
Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing #WE to logic low state; while #CE is at logic low state and #OE is at logic high state. Addresses are latched on the falling edge of #WE or #CE, whichever happens later; while data is latched on the rising edge of #WE or #CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Program Waveforms for specific timing parameters.
6.1.3
Standby Mode
The Standby mode is achieved with the #CE input held at VDD 0.3V and the current is typically reduced to
less than 5A (max). In the standby mode the outputs are in the high impedance state, independent of the #OE input.
6.1.4
Output Disable Mode
With the #OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high impedance state.
6.1.5
Auto-select Mode
The auto-select mode allows the reading of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (11.5V to 12.5V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All addresses are dont cares except A0 and A1 (see "Auto-select Codes"). The manufacturer and device codes may also be read via the command register, for instance, when the W39L040A is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in "Auto-select Codes".
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Byte 0 (A0 = VIL) represents the manufacturers code (Winbond = DAH) and byte 1 (A0 = VIH) the device identifier code (W39L040A = D6hex). All identifiers for manufacturer and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the Auto-select, A1 must be low state.
6.2 Data Protection
The W39L040A is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VDD power-up and power-down transitions or system noise.
6.2.1
Low VDD Inhibit
To avoid initiation of a write cycle during VDD power-up and power-down, the W39L040A locks out when VDD < 2.0V (see DC Characteristics section for voltages). The write and read operations are inhibited when VDD is less than 2.0V typical. The W39L040A ignores all write and read operations until VDD > 2,0V. The user must ensure that the control pins are in the correct logic state when VDD > 2.0V to prevent unintentional writes.
6.2.2
Write Pulse "Glitch" Protection
Noise pulses of less than 10 nS (typical) on #OE, #CE, or #WE will not initiate a write cycle.
6.2.3
Logical Inhibit
Writing is inhibited by holding any one of #OE = VIL, #CE = VIH, or #WE = VIH. To initiate a write cycle #CE and #WE must be a logical zero while #OE is a logical one.
6.2.4
Power-up Write and Read Inhibit
Power-up of the device with #WE = #CE = VIL and #OE = VIH will not accept commands on the rising edge of #WE except 5mS delay (see the power up timing in AC Characteristics). The internal state machine is automatically reset to the read mode on power-up.
6.3 Command Definitions
Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. "Command Definitions" defines the valid register command sequences.
6.3.1
Read Command
The device will automatically power-up in the read state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. The device will automatically returns to read state after completing an Embedded Program or Embedded Erase algorithm. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. -6-
W39L040A
6.3.2 Auto-select Command
Flash memories are intended for use in applications where the local CPU can alter memory contents. As such, manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally a desirable system design practice. The device contains an auto-select command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the auto-select command sequence into the command register. Following the command write, a read cycle from address XX00H retrieves the manufacture code of DAH. A read cycle from address XX01H returns the device code (W39L040A = D6hex). To terminate the operation, it is necessary to write the auto-select exit command sequence into the register.
6.3.3
Byte Program Command
The device is programmed on a byte-by-byte basis. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two "unlock" write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded program algorithm. Addresses are latched on the falling edge of #CE or #WE, whichever happens later and the data is latched on the rising edge of #CE or #WE, whichever happens first. The rising edge of #CE or #WE (whichever happens first) begins programming using the Embedded Program Algorithm. Upon executing the algorithm, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The automatic programming operation is completed when the data on DQ7 (also used as #Data Polling) is equivalent to the data written to this bit at which time the device returns to the read mode and addresses are no longer latched (see "Hardware Sequence Flags"). Therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time for #Data Polling operations. #Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a hardware reset occurs during the programming operation, the data at that particular location will be corrupted. Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be programmed back to a "1". Attempting to program 0 back to 1, the toggle bit will stop toggling. Only erase operations can convert "0"s to "1"s. Refer to the Programming Command Flow Chart using typical command strings and bus operations.
6.3.4
Chip Erase Command
Chip erase is a six-bus-cycle operation. There are two "unlock" write cycles, followed by writing the "set-up" command. Two more "unlock" write cycles are asserted, followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device will automatically erase and verify the entire memory for an all one data pattern. The erase is performed sequentially on each sectors at the Publication Release Date: April 14, 2005 Revision A3
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W39L040A
same time (see "Feature"). The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last #WE pulse in the command sequence and terminates when the data on DQ7 is "1" at which time the device returns to read the mode. Refer to the Erase Command Flow Chart using typical command strings and bus operations.
6.3.5
Sector Erase Command
Sector erase is a six-bus-cycle operation. There are two "unlock" write cycles, followed by writing the "set-up" command. Two more "unlock" write cycles then follows by the sector erase command. The sector address (any address location within the desired sector) is latched on the falling edge of #WE, while the command (30H) is latched on the rising edge of #WE. Sector erase does not require the user to program the device prior to erase. When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The automatic sector erase begins after the erase command is completed, right from the rising edge of the #WE pulse for the last sector erase command pulse and terminates when the data on DQ7, #Data Polling, is "1" at which time the device returns to the read mode. #Data Polling must be performed at an address within any of the sectors being erased. Refer to the Erase Command flow Chart using typical command strings and bus operations.
6.4 Write Operation Status
6.4.1 DQ7: #Data Polling
The W39L040A device features #Data Polling as a method to indicate to the host that the embedded algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an attempt to read the device will produce a "1" at the DQ7 output. For chip erase, the #Data Polling is valid after the rising edge of the sixth pulse in the six #WE write pulse sequences. For sector erase, the #Data Polling is valid after the last rising edge of the sector erase #WE pulse. #Data Polling must be performed at sector addresses within any of the sectors being erased. Otherwise, the status may not be valid. Just prior to the completion of Embedded Algorithm operations DQ7 may change asynchronously while the output enable (#OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of time and then that bytes valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operations and DQ7 has a valid data, the data outputs on DQ0 - DQ6 may be still invalid. The valid data on DQ0 - DQ7 will be read on the successive read attempts. The #Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm, or sector erase time-out (see "Command Definitions").
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W39L040A
6.4.2 DQ6: Toggle Bit
The W39L040A also features the "Toggle Bit" as a method to indicate to the host system that the embedded algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (#OE toggling) data from the device at any address will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempt. During programming, the Toggle Bit is valid after the rising edge of the fourth #WE pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid after the rising edge of the sixth #WE pulse in the six write pulse sequence. For sector erase, the Toggle Bit is valid after the last rising edge of the sector erase #WE pulse. The Toggle Bit is active during the sector erase time-out. Either #CE or #OE toggling will cause DQ6 to toggle.
6.5 Table of Operating Modes
6.5.1 Device Bus Operations
PIN
(VID = 12 0.5V)
MODE
#CE Read Write Standby
Write Inhibit
#OE #WE VIL VIH X VIL
X
A0 A0 A0 X X X X VIL VIH
A1 A1 A1 X X X X VIL VIL
A9 A9 A9 X X X X VID VID
DQ0 - DQ7 Dout Din High Z
High Z/Dout High Z/Dout
VIL VIL VIH
X X
VIH VIL X
X
VIH VIH VIH VIH
Output Disable Auto select Manufacturers ID Auto select Device ID
VIL VIL VIL
VIH VIL VIL
High Z Code Code
6.5.2
Auto-select Codes (High Voltage Method)
DESCRIPTION #CE #OE #WE A9 THE OTHER ADDRESS DQ[7:0]
(VID = 12 0.5V)
Manufacturer ID: Winbond Device ID: W39L040A
VIL VIL
VIL VIL
VIH VIH
VID VID
All Address = VIL A1 = VIH, All other = VIL
DAhex D6hex
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6.5.3 Sector Address Table
A18 A17 A16 SECTOR SIZE (KBYTES) ADDRESS
SECTOR
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
64 64 64 64 64 64 64 64
00000h - 0FFFFh 10000h - 1FFFFh 20000h - 2FFFFh 30000h - 3FFFFh 40000h - 4FFFFh 50000h - 5FFFFh 60000h - 6FFFFh 70000h - 7FFFFh
Note: All sectors are 64K bytes in size.
6.5.4
Command Definitions
NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE Cycles Addr. (1) Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data 1 6 6 4 3 3 1
(2) (2)
COMMAND DESCRIPTION Read Chip Erase Sector Erase Byte Program Product ID Entry Product ID Exit Product ID Exit
AIN 5555 5555 5555 5555 5555 XXXX
DOUT AA AA AA AA AA F0 2AAA 2AAA 2AAA 2AAA 2AAA 55 55 55 55 55 5555 5555 5555 5555 5555 80 80 A0 90 F0 5555 5555 AIN AA AA DIN 2AAA 2AAA 55 55 5555 SA
(3)
10 30
Notes: 1. Address Format: A14 - A0 (Hex); Data Format: DQ7 - DQ0 (Hex) 2. Either one of the two Product ID Exit commands can be used. 3. SA: Sector Address SA = 7XXXXh for Unique Sector7 SA = 6XXXXh for Unique Sector6 SA = 5XXXXh for Unique Sector5 SA = 4XXXXh for Unique Sector4 SA = 3XXXXh for Unique Sector3 SA = 2XXXXh for Unique Sector2 SA = 1XXXXh for Unique Sector1 SA = 0XXXXh for Unique Sector0 4. XX: Don't care
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W39L040A
6.6 Embedded Programming Algorithm
Start
Write Program Command Sequence (see below)
#Data Polling/ Toggle bit
Pause T BP
No Increment Address Last Address ? Yes Programming Completed
Program Command Sequence (Address/Command):
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
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6.7 Embedded Erase Algorithm
Start
Write Erase Command Sequence (see below)
#Data Polling or Toggle Bit Successfully Completed
Pause TEC/TSEC/TPEC
Erasure Completed
Chip Erase Command Sequence (Address/Command): 5555H/AAH
Individual Sector Erase Command Sequence (Address/Command): 5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/80H
5555H/80H
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/10H
Sector Address/30H
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W39L040A
6.8 Embedded #Data Polling Algorithm
Start
VA = Byte address for programming = Any of the sector addresses within the sector being erased during sector erase operation = Any of the device addresses being erased during chip erase operation
Read Byte (DQ0 - DQ7) Address = VA
No
DQ7 = Data ? Yes Pass
6.9 Embedded Toggle Bit Algorithm
Start
Read Byte (DQ0 - DQ7) Address = Don't Care
Yes
DQ6 = Toggle ? No Pass
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7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
PARAMETER RATING UNIT
Operating Temperature Storage Temperature Power Supply Voltage to VSS Potential Voltage on Any Pin to Ground Potential except A9 Voltage on A9, #OE Pin to Ground Potential
0 to +70 -65 to +150 -0.5 to VDD+0.5 -0.5 to +4.0 -0.5 to +12.5
C C V V V
Note: Exposure to conditions beyond those listed under Absolute maximum Ratings may adversely affect the life and reliability of the device.
7.2 DC Operating Characteristics
(VDD = 3.0 ~ 3.6V for 70 nS or VDD = 2.7 ~ 3.6V for 90 nS, VSS = 0V, TA = 0 to 70 C)
PARAMETER
SYM.
TEST CONDITIONS MIN.
LIMITS TYP. MAX.
UNIT
Power Supply Read Current Power Supply Write Current Standby VDD Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
IDD1 IDD2 ISB ILI ILO VIL VIH VOL
#CE = VIL, #OE = VIH, at f = 5 MHz #CE = VIL, #OE = VIH #CE = VDD 0.3V VIN = VSS to VDD, VDD = VDD max. VOUT = VSS to VDD, VDD = VDD max. IOL = 4.0 mA, VDD = VDD min.
-0.5 0.7 x VDD 0.85 VDD VDD -0.4
7 15 0.2 -
12 30 5 1 1 0.8 VDD +0.3 0.45 -
mA
mA A
A A V V V V V
VOH1 IOH = -2.0 mA, VDD = VDD min. VOH2 IOH = -100 A, VDD = VDD min.
7.3 Pin Capacitance
(VDD = 3.3V for 70 nS, or VDD = 3.0V for 90 nS, TA = 25 C, f = 1 MHz)
PARAMETER
SYMBOL
CONDITIONS
TYP.
MAX.
UNIT
Input Capacitance Output Capacitance
CIN COUT
VIN = 0V VOUT = 0V
6 8.5
7.5 12
pF pF
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W39L040A
7.4 AC Characteristics
7.4.1 AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load
0V to 3.0V <5 nS 1.5V/1.5V 1 TTL Gate CL = 30pF for 70nS/ 100pF for 90nS
7.4.2
AC Test Load and Waveform
+3.3V
1.2K
DOUT
30 pF for 70nS 100 pF for 90nS (Including Jig and Scope)
2.1K
Input
3V 1.5V 0V Test Point
Output
1.5V
Test Point
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AC Characteristics, continued
7.4.3
Read Cycle Timing Parameters
70 nS MIN. MAX. 70 70 30 16 16 90 nS MIN. 90 0 MAX. 90 90 35 16 16 nS nS nS nS nS nS nS
(VDD = 3.0 ~ 3.6V for 70 nS or VDD = 2.7 ~ 3.6V for 90 nS, VSS = 0V, TA = 0 to 70 C)
PARAMETER Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time #CE High to High-Z Output #OE High to High-Z Output Output Hold from Address Change
SYM.
UNIT
TRC TCE TAA TOE TCHZ TOHZ TOH
70 0
7.4.4
Erase/Program Cycle Timing Parameters
PARAMETER SYM. MIN. 70 nS TYP. 9 4.5 6 0.7 MAX. 200 13.5 50 6 MIN. 90 0 45 0 0 0 35 30 45 0 90 nS TYP. 9 4.5 6 0.7 MAX. 200 13.5 50 6 nS nS nS nS nS nS nS nS nS nS
S
UNIT
Write Cycle Time Address Setup Time Address Hold Time #CE Setup Time #CE Hold Time #OE Setup Time #WE Pulse Width #WE High Width Data Setup Time Data Hold Time Byte Programming Time Chip Programming Time Chip Erase Cycle Time Sector Erase Cycle Time
TWC TAS TAH TCS TCH TOES TWP TWPH TDS TDH TBP TCP TEC TEP
70 0 45 0 0 0 35 30 35 0 -
S S S
Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.
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W39L040A
AC Characteristics, continued
7.4.5
Power-up Timing
PARAMETER SYMBOL TYPICAL UNIT
Power-up to Read Operation Power-up to Write Operation
TPU. READ TPU. WRITE
100 5
S mS
7.4.6
#Data Polling and Toggle Bit Timing Parameters
PARAMETER SYM. MIN.
70 nS 90 nS
UNIT MAX.
90 90 nS nS nS nS
MAX.
70 70
MIN.
10 10 -
#OE to #Data Polling Output Delay #CE to #Data Polling Output Delay #OE to Toggle Bit Output Delay #CE to Toggle Bit Output Delay
TOEP TCEP TOET TCET
10 10 -
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8. TIMING WAVEFORMS
8.1 Read Cycle Timing Diagram
T RC Address A18-0 TCE #CE
TOE #OE TOLZ TOHZ
VIH #WE
TCLZ High-Z DQ7-0
T OH Data Valid TAA
TCHZ High-Z Data Valid
8.2 #WE Controlled Command Write Cycle Timing Diagram
TAS Address A18-0
TAH
TCS #CE TOES #OE TWP #WE TDS DQ7-0 Data Valid
TCH TOEH
TWPH
TDH
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W39L040A
Timing Waveforms, continued
8.3 #CE Controlled Command Write Cycle Timing Diagram
TAS
TAH
Address A18-0 TCPH TCP #CE TOES #OE TOEH
#WE TDS DQ7-0 High Z Data Valid
TDH
8.4 Chip Erase Timing Diagram
Six-byte code for 3.3V-only software chip erase Address A18-0 5555 2AAA 5555 5555 2AAA 5555
DQ7-0
AA
55
80
AA
55
10
#CE
#OE TWP #WE SB0 TWPH SB1 SB2 SB3 SB4 SB5 Internal Erase starts TEC
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Publication Release Date: April 14, 2005 Revision A3
W39L040A
Timing Waveforms, continued
8.5 Sector Erase Timing Diagram
Six-byte commands for 3.3V-only Sector Erase Address A18-0 5555 2AAA 5555 5555 2AAA SA
DQ7-0
AA
55
80
AA
55
30
#CE
#OE TWP #WE SB0 SA = Sector Address TWPH SB1 SB2 SB3 SB4 SB5 Internal Erase starts TEP
8.6 #Data Polling Timing Diagram
Address A18-0
An
An
An
An
#WE TCEP #CE TOEH #OE TOEP DQ7 X X TBP or TEC X X TOES
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W39L040A
Timing Waveforms, continued
8.7 Toggle Bit Timing Diagram
Address A18-0
#WE
#CE TOEH #OE TOES
DQ6 TBP orTEC
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Publication Release Date: April 14, 2005 Revision A3
W39L040A
9. ORDERING INFORMATION
PART NO. ACCESS TIME (nS) POWER SUPPLY CURRENT MAX. (mA) STANDBY VDD CURRENT MAX. (A) PACKAGE OPERATIN G TEMP. CYCLE (C)
W39L040AP70B W39L040AP90B W39L040AQ70B W39L040AQ90B W39L040AT70B W39L040AT90B W39L040A70B W39L040A90B W39L040AT70Z W39L040AT90Z W39L040AP70Z W39L040AP90Z
Notes:
70 90 70 90 70 90 70 90 70 90 70 90
12 12 12 12 12 12 12 12 12 12 12 12
5 5 5 5 5 5 5 5 5 5 5 5
32L PLCC 32L PLCC 32L STSOP (8x14 mm) 32L STSOP (8x14 mm) 32L TSOP (8 x 20 mm) 32L TSOP (8 x 20 mm) 32L PDIP 32L PDIP 32L TSOP (8 x 20 mm) Lead free 32L TSOP (8 x 20 mm) Lead free 32L PLCC Lead free 32L PLCC Lead free
0 - 70 0 - 70 0 - 70 0 - 70 0 - 70 0 - 70 0 - 70 0 - 70 0 - 70 0 - 70 0 - 70 0 - 70
10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K
1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
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W39L040A
10. HOW TO READ THE TOP MARKING
Example: The top marking of 32-pin TSOP W39L040AT-70
W39L040AT70B 2138977A-A12 325OBFA
1st line: Winbond logo 2nd line: the part number: W39L040AT70B 3rd line: the lot number 4th line: the tracking code: 325 O B SA 325: Packages made in '03, week 25 O: Assembly house ID: A means ASE, O means OSE, ...etc. B: IC revision; A means version A, B means version B, ...etc. FA: Process code
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Publication Release Date: April 14, 2005 Revision A3
W39L040A
11. PACKAGE DIMENSIONS
11.1 32L PLCC
HE E
4
1
32
30
Symbol
5 29
Dimension in Inches
Dimension in mm
Min.
0.020 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075
Nom.
Max.
0.140
Min.
0.50
Nom.
Max.
3.56
GD D HD
13
21
14
20
c
A A1 A2 b1 b c D E e GD GE HD HE L y Notes:
0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.510 0.410 0.590 0.490 0.090
0.115 0.032 0.022 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.004
2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91
2.80 0.71 0.46 0.25 13.97 11.43 1.27 12.95 10.41 14.99 12.45 2.29
2.93 0.81 0.56 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.10
0
10
0
10
L A2 A
Seating Plane
e
b b1 GE
A1 y
1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on final visual inspection sepc.
11.2 32L PDIP
Dimension in inches
Symbol
Dimension in mm
Min. Nom. Max. Min. Nom. Max.
0.210 0.010 0.150 0.016 0.048 0.008 0.155 0.018 0.050 0.010 1.650 0.590 0.545 0.090 0.120 0 0.630 0.650 0.600 0.550 0.100 0.130 0.160 0.022 0.054 0.014 1.660 0.610 0.555 0.110 0.140 15 0.670 0.085 14.99 13.84 2.29 3.05 0 16.00 16.51 0.25 3.81 0.41 1.22 0.20 3.94 0.46 1.27 0.25 41.91 15.24 13.97 2.54 3.30 4.06 0.56 1.37 0.36 42.16 15.49 14.10 2.79 3.56 15 17.02 2.16 5.33
D
32 17
E1
A A1 A2 B B1 c D E E1 e1 L
a
1
16
eA S Notes:
E c
S
A A2 L B B1
A1
Base Plane Seating Plane
e1
a
eA
1.Dimensions D Max. & S include mold flash or tie bar burrs. 2.Dimension E1 does not include interlead flash. 3.Dimensions D & E1 include mold mismatch and . are determined at the mold parting line. 4.Dimension B1 does not include dambar protrusion/intrusion. 5.Controlling dimension: Inches 6.General appearance spec. should be based on final visual inspection spec.
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W39L040A
11.3 32L TSOP (8 x 20 mm)
HD
Symbol
Dimension in Inches Min. Nom. Max.
0.047 0.006 0.041 0.009 0.007 0.728 0.319 0.795
Dimension in mm Min. Nom. Max.
1.20 0.15 1.05 0.23 0.17 18.50 8.10 20.20
D c
A A1 A
2
__
0.002 0.037 0.007 0.005 0.720 0.311 0.780
__ __
0.039 0.008 0.006 0.724 0.315 0.787 0.020 0.020 0.031
__
0.05 0.95 0.17 0.12 18.30 7.90 19.80
__ __
1.00 0.20 0.15 18.40 8.00 20.00 0.50 0.50 0.80
M
e E
b c D
0.10(0.004)
b
E HD e L L
A A2 L L1 A1
1
__
0.016
__
0.024
__
0.40
__
0.60
__
0.000 1
__
0.004 5
__
0.00 1
__
0.10 5
Y
__
3
__
3
Y
Note:
Controlling dimension: Millimeters
11.4 32L STSOP (8 x 14 mm)
HD D c
Dimension in Inches Dimension in mm Symbol Min. Nom. Max.
0.047 0.002 0.035 0.007 0.004 0.040 0.009 ----0.488 0.315 0.551 0.020 0.020 0.024 0.031 0.000 0 3 0.004 5 0.00 0 3 0.028 0.50 0.006 0.041 0.010 0.008 0.05 0.95 0.17 0.10 1.00 0.22 ----12.40 8.00 14.00 0.50 0.60 0.80 0.10 5 0.70
Min. Nom. Max.
1.20 0.15 1.05 0.27 0.21
e
E
b
A A1 A2 b c D E HD e L L1 Y
L L1
A1 A2 A
Y
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Publication Release Date: April 14, 2005 Revision A3
W39L040A
12. VERSION HISTORY
VERSION DATE PAGE DESCRIPTION
A1 A2 A3
Sep. 24, 2004 Nov. 25, 2004 April 14,2005
3, 24, 25 26
Initial Issued Added 32L PDIP and 32L TSOP package dimensions Add important notice
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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